If you’re involved in designing or manufacturing chips, you’re in the front row watching two simultaneous and independent trends that are causing big challenges both for you and for the folks building systems out of your ICs.
The first trend is the electrification of systems that may have fatal outcomes if they fail. Historically, this has been a consideration for systems that are clearly safety-critical, like automobiles and airplanes with their “drive-by-wire” and “fly-by-wire” initiatives. But, increasingly, electronics are showing up in all kinds of systems everywhere, and these devices will be widely interconnected. So even a failure within an innocuous-seeming system could lead, through a chain of interactions, to a serious negative outcome, like a service outage.
The second trend comes from the complexity of advanced silicon process nodes, making it much harder to hit aggressive performance, power, and cost targets. Process-parameter variation makes your job even harder.
Put these two trends together, and you have safety-critical systems containing semiconductor chips that have been built on the most advanced silicon process nodes. The increasing risk of failure and harm creates a need to monitor how each individual integrated circuit is operating. This will help with three critical phases of a chip’s life.
In order to make such monitoring possible, we need to start at chip design. This is when Agents are inserted into the design:low footprint circuits embedded into the chip, with corresponding algorithms placed in a server residing in a cloud or server farm. proteanTecs’ patented technology determines, through detailed analysis of process parameter variability and design models, the type and in-chip location of these Agents.
Agents take direct parametric measurements and communicate them to a cloud-based analytics platform through existing communication channels on the testers or in the systems. Machine learning is applied to convert the raw measurements into intelligence that lets any number of stakeholders take action where and when needed. The aggregated data will reflect the entire lifecycle of the chip, from design and manufacturing through its life in the field.
Depending on where you are in the lifecycle, you can
Each individual chip can be monitored from production through its useful life. Adverse events can be anticipated before they happen.
Chip manufacturers can feed measurements from early in the lifecycle forward, helping to drive decisions as to whether, for example, a specific marginal device should be used in a particular system or perhaps reserved for some less-demanding system. This can be an effective way of avoiding possible expensive system recalls.
Manufacturing engineers can feed ongoing learning from any field failures back into the manufacturing line to speed identification of root-cause corrections, improving the quality and reliability of subsequent chips. Process engineers can also use that data to improve the design models that you use during design verification. System integrators will be comforted not only by the increased manufacturing scrutiny, but also by the ongoing monitoring that will provide a heads-up before anything goes wrong in the field.