Deep analysis. Deep data. Deep insights.
During chip design, hundreds of possible manufacturing variants are modeled for each specific design, creating a complete production view and providing insights into the chip's performance, power and parametric yields.
During chip design, Agents are seamlessly embedded, without penalty, based on an automated and thorough design analysis, to create high coverage novel data on the chip’s profiling, health and performance.
After Tape-Out and before chip production, design simulations across hundreds of manufacturing model variants are generated, uploaded to the software platform and processed by machine learning algorithms.
During chip and system production and while in-field, analytics are applied to the Agent Readouts for data fusion and actionable insights & alerts are provided by the software platform.
Actionable insights and alerts on a cloud-based analytics platform
Outlier detection without compromising yield
Alerts on faults before failures
Faster detection of systematic issues
Faster time to volume production at a higher level of certainty
Apples-to-apples correlation of silicon to design simulations
High resolution binning at Wafer Sort
Early detection of faults with pinpointed source identification
Margin visibility for predictive design, production and deployment
Universal Chip Telemetry (UCT) is a new standard that quantifies the value, as measured by performance monitoring, quality, reliability and cost, based on embedded Agents. It creates a common measure across the value chain. The UCT level is determined by the coverage and variety of Agents integrated.
IPs automatically tailored to represent and cover a specific design. Multi-dimensional Agent measurements create a plethora of novel data fused together to provide unprecedented visibility.
Classification of chips into "Families", which are groups of chips that have similar parametric behavior. Their characteristics are maintained across voltage and temperature conditions and while chips undergo transformations: on a wafer, packaged, or assembled on a system. “Family invariance” serves as an intrinsic basis for correlation, yield and quality improvements and fast, accurate performance binning.
Delay measurements of billions of paths, in parallel with normal operation, monitor performance at real application and degradation patterns. The Agents detect potential failures stemming from aging, reliability issues, latent defects that develop over time, environment and workload effects.
Detect events caused by device operation or environment and explain performance health source. Operational level fusion with performance monitoring and Family association provides unprecedented coverage and early pinpointed indication of hazards.