During chip design, hundreds of possible manufacturing variants are modeled for each specific design, creating a complete production view and providing insights into the chip's performance.
During chip design, Agents are seamlessly embedded, without penalty, based on an automated and thorough design analysis, to create high coverage novel data on the chip’s profiling, health and performance.
During chip and system production and use, machine learning is applied to data created by the Agents, and meaningful insights are provided by the software analytics platform.
Make better design decisions with Proteus-EDA, which provides insights about design sensitivities that impact performance.
Gain observations that improve Power/Performance/Area and Time-to-Volume, increase product competitiveness and reduce costs.
At the push of a button, gain insights from every and all chips for precise binning, high resolution outlier detection and increased observability to systematic production shifts and drifts.
Increase chip quality, at faster Time-to-Volume and lower costs.
High reliability coverage which alerts on faults before they become failures, achieving true predictive maintenance.
Prevent failures and epidemics and pinpoint the exact source of issues. Gain insights into electronics’ health, workload and performance, and manage performance and remaining useful life.
Based on novel data created by the Agents, the chip operates as a sensor reporting on the system’s health and performance.
Gain increased production efficiencies and improved product quality, while quickly identifying and locating issues that affect performance or delay production.
Classification of chips into Families, which are groups of chips that have similar parametric behavior. The Family classification is maintained across voltage and temperature conditions and while chips undergo transformations: on a wafer, packaged, or assembled on a system. “Family invariance” serves as an intrinsic basis for correlation, yield and quality improvements and fast, accurate performance binning.
Delay measurements of billions of paths, in parallel with normal operation, monitor degradation patterns and detect potential failures stemming from aging, reliability issues, latent defects that develop over time, environment and workload effects.
Detection of health and performance degradation caused by the chips’ system level feeds, connectivity and usage in that system. Operationl level fusion with performance monitoring and Family association provides unprecedented coverage and early indication of hazards.
Co-Founded and served as COO of Mellanox (NASDAQ: MLNX). Previously, senior staff member in the Pentium processors department at Intel.
Co-Founded and served as VP of Backend and Product Engineering at Mellanox (NASDAQ: MLNX). Technical manager in the processors department at Intel.
Co-Founded and served as SVP of Engineering at Mellanox (NASDAQ: MLNX). Previously, manager in Galileo Technologies and Intel.
Previously CEO of Broadlight (acquired by Broadcom). Held key R&D roles at Virata and IBM Research.
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