The era of chiplets and heterogeneous integration is here. High-end performance packaging will be a $7.87 billion market by 2027, with a 19% CAGR. (1)
As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law, it has created new challenges. How will we develop high speed and efficient interconnect protocols? What techniques do we need around post-packaging testing and the quality assurance of the assembled products? How will we monitor the reliability of the die-to-die (D2D) interconnects in mission mode? Emerging solutions are coming to light around how these challenges can be proactively addressed and solved, especially around visibility into high bandwidth D2D interfaces and advanced packaging.
This 40-minute webinar will offer 3 unique perspectives on this growing market and ecosystem: