High reliability applications in service-critical markets, such as autonomous driving and cloud computing, demand maximum performance and minimal power and cost. Reducing design margins while maintaining high reliability becomes imperative.

State-of-the-art silicon processes offer mainly logic density improvements at limited speedup. Worst-case design analysis is not cost effective anymore. Since devices degrade over time and sometimes abnormally, design margin analysis must be performed in an intelligent way and based on actual in-situ margin measurements. Targeted deep data with end-to-end health monitoring is needed to achieve scale in the era of mega-functionality.  

proteanTecs’ on-chip monitoring and analytics solutions offer the ultimate tool to accomplish this reliability, yield, performance, and power co-optimization. The company offers the monitor IP, the CAD flows and tools to facilitate the IP integration in the chip and make sure the implementation will provide the expected value, as well as the machine learning algorithms and analytics SW stack to analyze the measured data at all phases of the product cycle; from wafer testing, packaged device testing, NPI, system ramp, system test and in field monitoring, until product retirement.

By downloading this whitepaper, you'll learn:

• How to push through the the power, frequency and performance wall that was hit several years ago, limiting the the chip lifetime functionality, and break the equation of trade-offs
• How proteanTecs seamlessly integrates into the design process, enabling efficient full chip control and providing essential analytics for chip and system characterization, production, and operation, including real-world field conditions
• How the proteanTecs analytics leverage intelligent ML algorithms to monitor critical paths, real application workloads, operational effects and design sensitivities