proteanTecs Solution - Advanced Packaging

Advanced Packaging

Ensure chiplet and die-to-die interconnect health, performance, and reliability across production and in-field operation.

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15%: Lower SiP Costs

5%: Higher Packaging Yield

10X: Lower Interconnect DPPM

Shift Left Decisions

Take predictive actions before packaging and SiP assembly.

Enables early detection of outliers, improving yield and preventing costly packaging of marginal dies. Reduce iterative testing, maintain die inventory instead of packaged chips, and lower overall packaging and SiP costs while improving end-product quality.

Chiplet Mix & Match

Enables smart KGD selection and binning to improve test quality early in the flow.

Gain parametric grading of power consumption, leakage, speed and more at Wafer Sort. Optimize yield and streamline inventory through smart die matching.

In-Mission Chiplet Monitoring

Continuously monitor chiplet health and performance in the field to reduce power, prevent failures, optimize throughput, and enable predictive maintenance.

Applicable across heterogeneous systems - including CPU, GPU, NPU, switches, IO dies, and custom HBM logic - this approach ensures smarter, data-driven SiP deployment at scale.

Understand Interconnect Behavior

Gain deep insight into how high-bandwidth interconnects behave under real operating conditions.

Parametric characterization enables per-lane grading of eye width, jitter, skew, and margin, providing the data needed to optimize design, test coverage, and interconnect quality.

Detect Marginality Early

Identify marginal lanes and latent defects that traditional pass or fail testing cannot expose.

Early outlier detection on the ATE supports lane grading and targeted lane repair, including the use of spare lanes or module-level decisions, to improve yield and prevent downstream escapes.

Monitor Degradation Over Time

Continuously track interconnect health during operation to detect degradation before it leads to failure.

In-mission monitoring enables timely alerts, spare lane activation, and module swap decisions to maintain reliability and extend system lifetime.

WHAT OUR CUSTOMERS ARE SAYING

"proteanTecs’ technology will accelerate our product development cycle and give us the confidence to scale quickly. Additionally, our customers will benefit from system in-field monitoring, as we are dealing with highly advanced electronics in uptime-sensitive markets."

June Paik • CEO, FuriosaAI

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"proteanTecs on-chip monitoring analytics adds a deeper layer of insights into our robust testing and verification program"

Kalyan Mulam • SVP of ASIC Engineering, Astera Labs

"proteanTecs is the only company today offering comprehensive visibility into high bandwidth D2D interfaces. Their high-resolution interconnect monitoring solutions deliver parametric lane grading with 100-percent lane and pin coverage, empowering us with critical insights that both accelerate and enhance our device testing and characterization, and offer our customers in-mission lifetime monitoring."

Igor Elkanovich • CTO, GUC

"proteanTecs’ technology is a game-changer for SoC time-to-volume. We embed the solution into our most advanced, high-performance ASIC designs to enable predictive monitoring that detects problems ahead of time. The result is increased parametric yield, decreased test time and power/performance optimization."

Johnny Shen • President and CEO, AIchip Technologies

common questions & answers

FAQ

Get answers to common questions about how proteanTecs enables shift-left decisions, improves yield, and ensures reliability for advanced packaging and chiplet-based SiPs.

Heterogeneous integration and advanced packaging introduce new failure modes that traditional test and validation cannot detect. proteanTecs closes this visibility gap by embedding deep, in-situ monitoring into chiplets, PHYs, and die-to-die interconnects, enabling early outlier detection, yield improvement, and long-term reliability assurance across the entire SiP lifecycle.
proteanTecs supports leading advanced packaging and heterogeneous integration flows, including CoWoS, InFO, EMIB, AIB, OpenHBI, Bow, and other 2.5D/3D SiP architectures. The solution is designed to be packaging-agnostic and scales across chiplet-based designs using standards such as UCIe and high-bandwidth memory interfaces including HBM4.
By shifting quality and reliability decisions earlier, before packaging and SiP assembly, proteanTecs enables identification of marginal dies and interconnect outliers at wafer sort and early test stages. This prevents costly packaging of failing or degrading dies, reduces iterative testing, improves packaged yield, and allows customers to keep die inventory instead of packaged chips.
Die-to-die interconnect monitoring is enabled through Tile-Connectivity Agents (TCA) embedded directly inside PHYs, combined with dedicated software applications. These agents provide deep visibility into interconnect behavior, enabling per-lane characterization, early detection of marginality, and continuous monitoring of UCIe and HBM links during both production and in-field operation.
Core Agents are embedded inside chiplets and custom logic dies. They profile designs, classify silicon behavior, monitor performance and performance degradation, and track operational and environmental effects such as voltage, temperature, and workload stress. This enables data-driven decisions across production, qualification, and mission-mode operation.
To learn more, visit our technology page.
Absolutely. proteanTecs supports end-to-end monitoring, from wafer sort and package assembly to system bring-up and in-mission operation. This ensures consistent visibility into chiplet and interconnect health throughout the full lifecycle of advanced packaged systems.
The solution enables parametric grading and outlier detection that go beyond pass/fail testing. By identifying subtle defects and latent risks early, customers can improve packaged yield, reduce interconnect DPPM, and significantly enhance overall SiP quality - especially in dense, high-bandwidth designs using UCIe and HBM4.
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proteanTecs supports a wide speed range from 2 GHz (4 Gb/s DDR) up to 8 GHz (16 Gb/s DDR). This enables accurate characterization, early outlier detection, and continuous monitoring across high-speed die-to-die interconnects, from bring-up and production test through in-mission operation.
Yes. proteanTecs’ technology is silicon-proven across advanced process nodes, including leading-edge and mature nodes used in chiplet-based and advanced packaging designs. The solution has been validated on real silicon with embedded Core Agents and Die-to-Die Interconnect Agents, demonstrating reliable monitoring, outlier detection, power reduction, and performance tracking across production and in-field operation for advanced interconnects such as UCIe and HBM-class (including HBM4) systems.

Advanced Packaging

Closing The Visibility Gap in SiP

End-to-End Chiplet and Die-to-Die Monitoring

Monitoring Built-In, From Die to PHY

Using In-Chip Monitoring and Deep Data Analytics for High Bandwidth Memory (HBM) Reliability and Safety

Data-Driven Heterogeneous Integration

Shift Left Decisions

Chiplet Mix & Match

In-Mission Chiplet Monitoring

Challenges and Emerging Solutions to
Support 2.5D and 3D Advanced Packaging

Ensuring Die-to-Die Interconnect Integrity

Understand Interconnect Behavior

Detect Marginality Early

Monitor Degradation Over Time

Interconnect Degradation Monitoring Demo

The Future of Chiplet Reliability: Interconnect Failure Prediction with 100% Lane Coverage

Industries

Discover More

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

Data Center Chipmaker Achieves 2.5D SOC Reliability with 100% Interconnect Coverage

Using In-Chip Monitoring and Deep Data Analytics for High Bandwidth Memory (HBM) Reliability and Safety

"proteanTecs’ technology will accelerate our product development cycle and give us the confidence to scale quickly. Additionally, our customers will benefit from system in-field monitoring, as we are dealing with highly advanced electronics in uptime-sensitive markets."

"proteanTecs on-chip monitoring analytics adds a deeper layer of insights into our robust testing and verification program"

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