proteanTecs and ELES have partnered together to enhance reliability testing with deep data analytics. This collaboration enables Soc manufacturers to improve their qualification envelope to achieve lifetime reliability, shorten their root cause analysis time, and reduce operational costs. This innovative approach adds parametric measurements during the stress test in order to accurately and precisely monitor the real degradation effects.
Reliability testing relies on industry-standard test methodologies, such as JEDEC JESD47 and JESD221. Traditionally, system-on-chip (SoC) devices are assembled on special boards and placed in the oven for accelerated lifetime stress, running unmonitored test patterns such as Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST), and are typically tested using normal test techniques outside the oven, at specified times.
However, these reliability testing procedures are mostly limited to pass/ fail conclusions and critical effects can be missed. Modern mission-critical applications, such as automotive and cloud computing, require going beyond these traditional IC testing methods to assure lifetime reliability, resilience and safety. They require the use of innovative approaches to guarantee the application of the adequate stress versus Mission Profile, to measure performance degradation more precisely and with fine granularity, simplifying the search for root cause analysis and enabling an effective design and manufacturing process improvement for Zero Defects.
This paper explores the benefits and improvements that can achieved by combining proteanTecs’ Health and Performance Monitoring solutions with ELES’ Design for Reliability methodology and advanced reliability test platforms.
By downloading this white paper, you’ll discover: