GUC GLink™ Test Chip Uses In-Chip Monitoring and Deep Data Analytics for High Bandwidth Die-to-Die Characterization

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With market growing demand for high performance products in mission critical, high bandwidth applications such as Automotive, AI/ML, 5G and more, the semiconductor industry must look for innovative technologies to continue scaling beyond the silicon manufacturing processes. This is often referred to as “More than Moore”, and one of the most promising methods is heterogenous integration of multiple dies inside the same package (System in Package, or SiP).

Key to success of the highly integrated SiP, is a high-performance interconnect. The two families of interconnect technologies are based on ultra-high data rate, low pin count serial interfaces (SERDES) or ultra-wide, high-density parallel interfaces. Of the two, parallel interfaces are gaining accelerated popularity due to their simplicity and flexibility in continuous scaling.

GUC’s GLink™ is a high bandwidth, low latency, and power efficient die-to-die interface. With power consumption of 0.3pJ/bit, up to 17Gbps single lane data rate and beachfront efficient of up to 2.5 Tbps/mm, GLink™ offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies.

With these technologies comes a plethora of challenges. Dies are assembled over the silicon interposer using very small micro-bumps which may suffer from latent defects such as voids or cracks, potentially posing a reliability risk to the assembled product. On organic substrates, rare resistive shorts, known as bridge-shorts, can cause signal integrity and performance degradation. These types of latent defects, although rare, could cause a system failure over time if not screened out during final test or detected during in-field operation.

Moreover, once the dies are assembled on the interposer or substrate, there is no practical way to test and assure that all thousands, sometimes over 10,000 lanes, are fully functional, defect-free and performing to spec.

proteanTecs provides a monitoring solution for heterogeneous packaging based on chip telemetry, combining deep data with machine learning algorithms. proteanTecs’ patent-protected solution is comprised of low footprint, digital-only agents for monitoring the performance of the parallel interface. These agents (monitoring IP) are designed for analytics. The fact that they have a low footprint, allows them to be placed next to each pin inside the parallel die-to-die (D2D) PHY, to achieve 100% coverage and with no impact on the signal behavior, quality or timing. Measurement data coming from the monitoring system is then extracted and ready for data analytics using proteanTecs cloud-based platform, where machine learning and dedicated algorithms are implemented to process the data, provide actionable insights, issue alerts, and visualize though customizable dashboards.

The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was to implement the proteanTecs monitoring system into the 5nm test chip to assist GUC in testing and characterizing the GLink PHY. proteanTecs is the only company today offering comprehensive visibility into high bandwidth die-to-die interfaces based on unique, patent-protected technology.

In this paper we present silicon results and conclusions from a GLink™ test chip developed by GUC which have integrated proteanTecs D2D monitoring technology on a 5nm chip.

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