Reliability Monitoring of GUC 7nm
High Bandwidth Memory (HBM) Subsystem

White Paper

Abstract

This white paper presents the use of proteanTecs’ Proteus™ for HBM subsystem reliability based on deep data analytics and enhanced visibility, overcoming the limitations of advanced heterogeneous packaging. It will describe the operation concept and provide results from a GUC 7nm HBM Controller ASIC.

A typical CoWoS chip has hundreds of thousands of micro-bumps (u-bumps). 3-8 u-bumps are used to route each of the signals or the power and ground. Due to the u-bump per signal redundancy, failure of a single u-bump may not necessarily affect the chip operation. However, an HBM PHY does not allow for redundancies due to the high-density routing, and one u-bump per signal is used for the entire HBM connectivity. In this case, a failure in any of the PHY or HBM u-bumps will lead to a chip operational failure. At testing, the implications of a failed module incur significant monetary losses for manufacturers. In lifetime (field) operation, a failure in the HBM subsystem may affect the whole system and lead to an abrupt operational failure and unplanned downtime.

Proteus demonstrated enhanced visibility for reliability monitoring and repair in GUC HBM subsystems. The results in this White Paper were collected using the GUC EX0010A testchip with Samsung’s memory Aquabolt, using worst case long zig-zag interposer connection and was tested at both 2.4 Gbps and 3.2 Gbps.

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