Advanced Packaging at Scale: Power, Performance and Reliability in the Chiplet Era
Design, test, and system teams need shift-left methodologies and new approaches to observability across chiplet lifecycles.
Design, test, and system teams need shift-left methodologies and new approaches to observability across chiplet lifecycles.
The transition to chiplet-based architectures, 2.5D integration, and system-in-package (SiP) designs is reshaping how the industry delivers performance and scalability. But as systems move beyond monolithic SoCs, new challenges emerge in power delivery, thermal behavior, mechanical integrity and package-level effects which are redefining system limits. At the same time, yield and cost pressures intensify as manufacturers move from Known-Good-Die (KGD) toward more complex multi-die assembly flows, including Known-Good-Stack (KGS).
In this online webinar, industry experts discuss how design, test, and system teams are adapting to these realities with shift-left methodologies and new approaches to observability across the lifecycle. From production test constraints and compound yield to limited visibility at die boundaries and in-field reliability/power targets, experts explore how the ecosystem is evolving to ensure robust, high-performance systems.
The webinar covers:
With targeted applications for performance monitoring, degradation monitoring and root-case analysis, predictive maintenance is enabled with a feedback mechanism to the supply chain. Designs, manufacturing processes, test programs, and in-field health tracking become hyper-personalized and predictive.
Predicting Final Test outcomes to reduce operational costs
In this webinar we describe and quantify the benefits of using deep data analytics to accelerate SoC product development. Rich Wawrzyniak of Semico Research presents a head-to-head comparison of two companies designing a similar multicore SoC on a 5nm technology node.