Semiconductors and Systems Built for Production Excellence
Accelerate bring-up, validation, and high-volume manufacturing of silicon and systems.
Accelerate bring-up, validation, and high-volume manufacturing of silicon and systems.
Design and develop devices for scale, with predictive hardware analytics and deep lab & test visibility.

Leverage telemetry-based analytics at Wafer Sort, Final Test, and System Level Test to improve quality, time-to-market, and operational efficiency.
Detect latent defects
Correlate between tests and stages
Pinpoint RMA analysis
Optimize characterization and qualification
Gain visibility of systems under functional workloads to monitor software and board impact on silicon performance.
Improve quality and reliability
Correlate silicon, system, and software behavior
Accelerate validation and deployment
Speed root-cause analysis


Optimize design guard bands, binning, and voltage margins using real workload telemetry.
Set static VDDmin per die
Improve binning accuracy
Optimize system VDD setting
Reduce test time
Ensure cost efficiency, reliability and performance of chiplets, 2.5D, and 3D packages during integration and production testing.
Shift left integration decisions
Increase packaging yield
Reduce interconnect DPPM
Accelerate time to market

Mohit Gupta • SVP and GM, Custom Silicon and IP, Alphawave
Eddie Ramirez • VP of Go-to-Market, Infrastructure Line of Business, Arm
Dr. Charlie Su • CTO and President, Andes Technology
June Paik • CEO, FuriosaAI
Kalyan Mulam • SVP of ASIC Engineering, Astera Labs
Ran Schrift • Director of Operations, Xsight Labs
Sue Ryu • CEO, SAPEON
Regan Mills • VP and General Manager, Semiconductor Test, Teradyne
Suk Lee • VP of Design Ecosystem Development, IFS
Michael Chang • VP and General Manager of ACS, Advantest
Suk Lee • VP of Design Ecosystem Development, IFS
Deep dive into our health and performance monitoring solutions for the next generation of SoC and Systems.
The Ultimate Solution for Reliability, Yield, Performance & Power Co-Optimization
This 1-hour panel discussion with industry experts from Qualcomm, Microsoft Azure and Advantest, discusses how data analytics and product insights can accelerate time to market and improve performance, yield and quality.
Two-stage detection approach, offering SDC prevention solutions for different stages of a chip's lifespan: ML-powered Outlier Detection for semiconductor defect detection and Real-Time Health Monitoring for in-field predictive and prescriptive maintenance.
This paper introduces proteanTecs groundbreaking Outlier Detection solution that eliminates that tradeoff. proteanTecs' Outlier Detection uses deep data analytics and ML to detect latent defects as early as Wafer Sort, achieving high fault detection accuracy by learning normal behavior with on-chip agents and comparing test measurements with predicted ones. It identifies marginal issues beyond simple pass/fail metrics, where traditional methods fail.
Discover how the fabless chipmaker used proteanTecs on-tester and cloud analytics to prevent a flood of RMAs with ML-powered spatial analysis