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FEATURED SESSION

Silicon-Aware Power Management for the Agentic AI Era

Presented by Dragon Hsu, GM Greater China, Senior Director of Application Engineering

This session introduces a silicon-aware approach that continuously measures each processor’s real-time timing margin, enabling hardware and software to make smarter decisions based on actual silicon conditions.

Attendees will learn how real-time timing-margin visibility:

• Reclaims voltage guard bands and improves frequency-voltage efficiency

• Increases AI workload throughput per watt

• Strengthens timing-failure protection across process, voltage, temperature, aging, and workload variations

What we're demonstrating

◆ In-Field Continuous Performance Monitoring Continuous telemetry from inside the chip, tracking performance, degradation, and variation across the product lifecycle, not just at test time.

◆ Workload-aware Power Reduction with AVS Pro Voltage adjustment based on what the chip is actually doing at any given moment, rather than worst-case assumptions baked in at design time.

◆ Product Bring-Up with Fast TTM In-silicon visibility that helps teams debug faster and reduce the back-and-forth between silicon and software during bring-up.

If you'd like dedicated time with our team at the show, fill in the form and we'll confirm a slot that works.

🎁 Come by the booth. We'll have something for you.