ON-DEMAND WEBINAR
The Era of Chiplets and Heterogeneous Integration
Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
This 40-minute webinar will offer 3 unique perspectives on this growing market and ecosystem from our panelists.
The era of chiplets and heterogeneous integration is here. High-end performance packaging will be a $7.87 billion market by 2027, with a 19% CAGR. (1)
The semiconductor industry is quickly adopting chiplets and heterogeneous integration for packaging as a key enabler to the continuation of scaling; yet it has created new challenges. How will we develop high speed and efficient interconnect protocols? What techniques do we need around post-packaging testing and the quality assurance of the assembled products? How will we monitor the reliability of the die-to-die (D2D) interconnects in mission mode? Emerging solutions are coming to light around how these challenges can be proactively addressed and solved, especially around visibility into high bandwidth D2D interfaces and advanced packaging.
Why chiplets are reshaping SoC design as rising costs and complexity push the industry beyond monolithic architectures
How 2.5D and 3D advanced packaging unlock the bandwidth, latency, and scalability chiplets require
What’s needed to make chiplets production-ready, from die-to-die interconnects to in-chip monitoring and validation
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This paper introduces proteanTecs groundbreaking Outlier Detection solution that eliminates that tradeoff. proteanTecs' Outlier Detection uses deep data analytics and ML to detect latent defects as early as Wafer Sort, achieving high fault detection accuracy by learning normal behavior with on-chip agents and comparing test measurements with predicted ones. It identifies marginal issues beyond simple pass/fail metrics, where traditional methods fail.