This 40-minute webinar will offer 3 unique perspectives on this growing market and ecosystem from our panelists.

The era of chiplets and heterogeneous integration is here. High-end performance packaging will be a $7.87 billion market by 2027, with a 19% CAGR.

The semiconductor industry is quickly adopting chiplets and heterogeneous integration for  packaging as a key enabler to the continuation of scaling; yet it has created new challenges. How will we develop high speed and efficient interconnect protocols? What techniques do we need around post-packaging testing and the quality assurance of the assembled products? How will we monitor the reliability of the die-to-die (D2D) interconnects in mission mode? Emerging solutions are coming to light around how these challenges can be proactively addressed and solved, especially around visibility into high bandwidth D2D interfaces and advanced packaging.

What you will learn

• Why chiplets are reshaping SoC design as rising costs and complexity push the industry beyond monolithic architectures

• How 2.5D and 3D advanced packaging unlock the bandwidth, latency, and scalability chiplets require

• What’s needed to make chiplets production-ready, from die-to-die interconnects to in-chip monitoring and validation