AI, HPC and Networking require integration of multiple dies (processors, networking, Serdeses, HBM memories) for high performance, modularity and yield. TSMC's 2.5D CoWoS technology is best fitted for high scale assembly. Short distance and fine pitch connectivity enable power, area and beachfront efficient interface. Many dies can be assembled with minimal power and area interfacing overhead.
As the complexity of 2.5D packaging continues to develop, reliability challenges arise. This is especially true in the interconnects between the SoC and HBM memories where high density prohibits duplicating connectivity. A new approach to reliability monitoring is emerging, for DPPM reduction and in-field failure prevention, based on Deep Data chip telemetry.
In this webinar, the operation concept of proteanTecs’ Proteus for High Bandwidth Memory (HBM) reliability will be discussed and results from a GUC 7nm HBM Controller ASIC will be presented.
Spanning a career of over 30 years, Igor Elkanovich served in technical leadership positions for numerous Semiconductors companies (Broadcom, Infineon, Freescale and others). Today, Igor serves as the CTO of Global Unichip (GUC). He is responsible for driving IP and methodology development using TSMC’s advanced silicon process and packaging technology while supervising definition and execution of large scale projects. His main focus is in Networking, AI and HPC applications.