AI, HPC and Networking require integration of multiple dies (processors, networking, Serdeses, HBM memories) for high performance, modularity and yield. TSMC's 2.5D CoWoS technology is best fitted for high scale assembly. Short distance and fine pitch connectivity enable power, area and beachfront efficient interface. Many dies can be assembled with minimal power and area interfacing overhead.

As the complexity of 2.5D packaging continues to develop, reliability challenges arise. This is especially true in the interconnects between the SoC and HBM memories where high density prohibits duplicating connectivity. A new approach to reliability monitoring is emerging, for DPPM reduction and in-field failure prevention, based on Deep Data chip telemetry.

In this webinar, the operation concept of proteanTecs’ Proteus for High Bandwidth Memory (HBM) reliability will be discussed and results from a GUC 7nm HBM Controller ASIC will be presented.

You’ll Learn:

• About HBM I/O and CoWoS bump quality monitoring in GUC’s 7nm and 5nm HBM2E PHYs
• How accuracy was validated in GUC’s 7nm and 5nm HBM2E testchips
• How to monitor quality in the field during normal chip operation
• How to prevent system operation failure and extend chip lifetime
• How to identify marginal IOs and CoWoS bumps via advanced analytics, long before HBM interface failure occurs
• How repair algorithms replace marginal IOs/ bumps with redundant ones at next boot cycle

‍

‍

‍