Live Webinar

From timing-margins to cache-misses in advanced SoCs

Monitoring parametric and logic-driven performance in production and in field
Jan 6 2021
12 pm EST | 5 pm GMT
40 Minutes
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You can now download the recorded webinar:

This webinar will introduce the concept of Deep Data performance monitoring and outline two highly complementary approaches that together form a comprehensive solution for performance optimization in development and production, and predictive maintenance in the field. This new combined approach tracks different ‘layers’ of the SoC to address key semiconductor industry pain points including design sensitivities; software and hardware bugs; device early-failure and wear-out; functional safety; and malicious attacks. It offers radical improvements in time-to-revenue, product quality, reliability and safety, and profitability.

Featuring use cases for ADAS performance optimization during test and in mission-mode.

Join us to learn:

+ How to predictively monitor safety, reliability and performance

+ How to optimize software interaction with hardware

+ How to obtain multi-layer predictive maintenance in the field

+ How to fine-tune applications in field-deployed systems

+ How to take the correct guard-bands for in-field operation

You’ll also have a chance to ask questions in a Q+A session at the end of the discussion.  

Can't make it? We’ve got you covered! Register anyway and we'll send you the recording afterwards.

We are sorry that you missed the live event. You can now download the recorded webinar:


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About the speakers

Gajinder Panesar, Fellow, Siemens Digital Industries Software

Gajinder Panesar is a Fellow at Mentor, A Siemens Business. One of Europe’s leading SoC architects, Gadge’s experience includes senior architecture definition and design roles within both blue-chip and start-up environments. He holds more than 20 patents and is the author of more than 20 published works. Gajinder was CTO at UltraSoC prior to the company’s acquisition by Mentor-Siemens. He has also held roles at NVIDIA (NASDAQ:NVDA); and Picochip, where he was Chief Architect, a role in which he continued after the company’s acquisition by Mindspeed Inc (NASDAQ:MSPD). His previous experience includes roles at STMicroelectronics, INMOS, and Acorn Computers. He is a former Research Fellow at the UK’s Southampton University, and a former Visiting Fellow at the University of Amsterdam.

Evelyn Landman, Co-Founder & CTO, proteanTecs

Evelyn Landman is an industry veteran and entrepreneur with over 30 years of semiconductor experience, owning a deep expertise in chip design and product engineering. Prior to founding proteanTecs, Evelyn co-founded Mellanox (NASDAQ: MLNX), a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage, where she served as VP of Backend and Product Engineering. Throughout her 17 years at Mellanox, Evelyn was responsible for IC backend design and production, systems and cables product engineering and in addition, led the company’s research group on assembly and optical technologies. From 1988-1999, Evelyn worked at Intel Corporation, where she was a senior staff member in the Processors department. Evelyn holds a B.Sc. cum laude in Electrical Engineering from The Israel Institute of Technology, Technion.

From timing-margins to cache-misses in advanced SoCs